As devices manufactured in semiconductor processes continue to shrink, certain characteristics of the smaller devices are less than optimal for certain types of applications. In particular, high frequency or radio frequency circuits, such as low noise amplifiers (LNAs) have demanding requirements on transistors. As devices sizes continue to shrink, the transistors of the advanced semiconductor processes exhibit increased leakage as the gate oxides become thinner, also short-channel effects may reduce performance of planar devices in advanced processes.
One area that promises improvement in transistor performance at deep submicron process nodes is the use of metal gates. Replacing conventional polysilicon gates with metal gates in MOS transistors can provide several advantages. Use of metal gates to replace the polysilicon gates can increase performance by increasing the gate field effect. Combining the metal gates with high-k gate dielectrics can improve transistor performance still further. The drive current can be increased, the source-drain leakage may be decreased, and the use of a thicker dielectric layer can also reduce gate leakage.
However, the resistance of the metal gate in such devices increases over the prior poly gates. Increased gate resistance has a negative impact in several areas. For example, the maximum oscillation frequency for a device is inversely proportional to the gate resistance Rg. Further, the noise factor for the device is directly proportional to the gate resistance. Thus, as the gate resistance increases, the noise factor increases, which is undesirable, while the maximum frequency decreases, which is also undesirable.
Known approaches to reduce metal gate resistance in conventional MOS FET transistors include providing a low resistance strap over the metal gate. For example, a metal-1 strap can be formed over the gate material. Multiple contacts may be used to couple the low resistance metal strap to the metal gate. However, known semiconductor process approaches for this structure can create defects such as etch damage in the metal gate. For the transistor, the use of the contacts over the active area can result in threshold voltage (“Vt”) variance that is negatively impacts the device performance, which is undesirable.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.